About
I'm a Formal Verification Engineer at Intel in Vancouver, BC. I work on pre-silicon verification of hardware IP blocks — writing SystemVerilog Assertions, building formal testbenches, running JasperGold proof campaigns, and driving coverage closure on digital designs across interconnect, protocol conversion, and hardware-firmware interface blocks.
My background is unusual for this field. Before moving to Canada in 2019, I spent over a decade as a public auditor and attorney in Brazil — work that was fundamentally about finding inconsistencies between a system's specified behaviour and its actual behaviour. Formal verification turns out to be the same problem, stated more precisely.
I hold a BSc in Computer Science from the University of British Columbia and am currently completing a Master of Engineering in Computer Engineering. I'm working toward P.Eng designation with Engineers and Geoscientists BC.
What I'm working on
- Deepening formal methods foundations — model checking theory, CTL/LTL, SAT/BDD
- Broadening tool exposure beyond JasperGold (VC Formal, Questa Formal)
- Building this site as a public record of things I've learned
- A formal verification project on an open-source RISC-V core (coming soon)